DE 10 2010 031 456 discloses a method for the safety-related disconnection of an electrical network, in which use is made of an interlock circuit (also called safety line loop, interlock or pilot line), the interruption of which disconnects an electrical energy source belonging to the electrical network or decouples it from the electrical network if there is a fear of danger to persons by live parts.
An interlock circuit which is in the form of a signal loop is therefore used in electrical networks, for example in vehicles, having a nominal voltage which exceeds 60 volts. The so-called interlock signal is generally generated using a so-called interlock generator in an energy source (for example in a battery) which supplies the electrical network with power. The signal is passed through all connectors of the electrical network and all components connected to the network, that is to say via passive and/or active so-called interlock participants. In this case, the system is configured in such a manner that, when a plug-in connection or a cover which prevents access to live parts is opened, the interlock circuit is inevitably interrupted. The signal is evaluated in all network participants which act as an energy source. If the interlock circuit is interrupted, each of these components disconnects the supply of energy into the network and possibly discharges the network. The typically required time between the interruption of the interlock circuit and the disconnection of the network protected by the latter is in the range below one second.
An interlock detector is usually situated at the end or else at another position of such an interlock circuit, which interlock detector is implemented in a battery control device, evaluates the interlock signal and supplies this evaluation to the battery control device.
FIG. 1 shows a basic circuit diagram of such an interlock detector implemented in an interlock detector system according to the prior art. In this case, the interlock detector 50 is connected to an interlock circuit 60 and to a microprocessor 30. In the interlock circuit 60, an interlock signal 26 is generated by an interlock generator 40, which signal is passed, in the interlock circuit 60, via an interlock circuit resistor 14, a measuring resistor 4 and optionally further active and/or passive interlock participants 7. The interlock signal 26 causes a defined voltage drop across the measuring resistor 4 of the interlock circuit 60. This defined voltage drop is tapped off via a differential amplifier 20 consisting of an operational amplifier 12 having a respective resistor 3, 6, 8 both in its two input branches and in its feedback branch, is possibly adapted to the signal level to be evaluated at an input branch of the operational amplifier 12 using an offset voltage Uref1 and is amplified. The amplified signal is supplied to a comparator circuit 10 via the output 13 of the differential amplifier 20. The comparator circuit 10 consists of two operational amplifiers 16, 18 in which an input of one operational amplifier 16 is connected to an input of the other operational amplifier 18. The signal passed to this connection 13 by the differential amplifier 20 is compared, by the first operational amplifier 16 of the comparator circuit 10, with an upper limit value Uref2 which is supplied to the unconnected input of the operational amplifier 16. The signal resulting from the evaluation of the comparison is supplied directly to the microprocessor 30 via the output 9 of the operational amplifier 16 of the comparator circuit 10. The signal passed to the connection 13 by the differential amplifier 20 is compared, by the second operational amplifier 18 of the comparator circuit 10, with a lower limit value which is supplied to the unconnected input of the operational amplifier 18. The signal resulting from the evaluation of the comparison is supplied directly to the microprocessor 30 via the output 24 of the operational amplifier 18 of the comparator circuit 10. The received signals are then evaluated in the microprocessor within an interval of time and are compared with a desired value.